Semiconductor IP and Design Licensing | Gurpreet S. Bal, Silicon Valley Technology Attorney

Semiconductor licensing is among the most technically complex and commercially consequential areas of technology law, encompassing IP core licenses from architecture providers, EDA tool compliance obligations, foundry process design kit agreements, patent pool licensing, and the increasingly acute intersection of semiconductor IP with U.S. export control law. Gurpreet S. Bal, a Partner at Foley and Lardner LLP in Silicon Valley, advises semiconductor companies, fabless design houses, and IP licensors on structuring transactions that navigate the full stack of legal obligations — from design-time licensing through manufacturing and ultimately to the FRAND dynamics that govern standard-essential patent portfolios in wireless and connectivity standards.

How do hard core vs. soft core IP licensing structures and royalty models work in semiconductors?

The first decision is whether to license a hard core, a fixed layout optimized for a specific foundry process, or a soft core, synthesizable RTL the licensee compiles for its target process. Hard cores offer predictable performance but bind the licensee to one foundry and node, while soft cores offer portability at the cost of optimization work and synthesis restrictions. The royalty models differ accordingly, with hard cores often carrying a per-unit royalty and soft cores an upfront access fee plus per-unit royalty, and field-of-use restrictions limiting the IP to specified product categories require ongoing compliance monitoring.

The foundational licensing decision for any company incorporating third-party processor or subsystem IP is whether to license a hard core (a fixed, technology-specific GDS-II layout optimized for a particular foundry process) or a soft core (synthesizable RTL that the licensee compiles for its target process). Hard core licenses offer predictable performance and area characteristics but bind the licensee to a specific foundry and process node, limiting portability. Soft core licenses offer flexibility — the same RTL can be retargeted across multiple foundries and nodes — but require the licensee to bear optimization costs and to comply with restrictions on the synthesis and modification of licensed RTL. Gurpreet Bal advises licensees that the royalty models for these two structures differ significantly: hard core licenses often involve a per-unit royalty (a fixed dollar amount or percentage of chip selling price) paid on each chip manufactured, while soft core licenses may involve an upfront technology access fee plus a per-unit royalty. Field-of-use restrictions — limiting the licensed IP to specified product categories (mobile, automotive, data center) — are standard in ARM, MIPS, and RISC-V commercial licenses and require careful compliance monitoring as the licensee's product portfolio evolves.

What compliance requirements do EDA tool licenses and foundry PDK agreements impose?

EDA tools are licensed on per-seat, per-server, or capacity-based models with license servers that monitor usage, and over-usage is a common compliance gap at growing design teams, so agreements should be audited annually against actual toolchain usage, especially after acquisitions. Foundry PDK licensing is a separate set of obligations: PDKs contain proprietary process parameters and design rules, and license terms typically restrict use to that foundry, prohibit transfer, and impose confidentiality that survives termination. A PDK license is therefore a binding commitment to a foundry relationship, which carries strategic implications for multi-sourcing or transitioning manufacturing.

Electronic design automation (EDA) tools from Synopsys, Cadence, and Siemens EDA are licensed on a per-seat, per-server, or capacity-based model, with license server software that monitors usage against contractual entitlements. EDA license audits are a regular enforcement mechanism for tool vendors, and over-usage — running more simulation or synthesis jobs than licensed seats permit — is a common compliance gap at growing design teams. Gurpreet S. Bal advises semiconductor companies that EDA license agreements should be audited annually against actual toolchain usage, particularly after acquisitions that bring additional design teams under the same entity and consolidate EDA entitlements. Process design kit (PDK) licensing from foundries (TSMC, Samsung, GlobalFoundries, Intel Foundry) is a separate and equally consequential set of obligations: PDKs contain the foundry's proprietary process parameters, design rules, and standard cell libraries, and the license terms typically restrict use to designs fabricated at that foundry, prohibit transfer to third parties, and impose strict confidentiality obligations that survive termination. The PDK license is thus a binding commitment to a foundry relationship — a point that has significant strategic implications for companies considering multi-sourcing or transitioning manufacturing to alternative foundries.

How do ITAR and EAR export controls apply to semiconductor IP licensing?

Export control compliance is mandatory in any semiconductor IP transaction involving foreign persons or entities. The EAR, administered by BIS, controls dual-use items including design tools, technical data, and technology, and IP cores, RTL, and design methodologies for advanced processors can require a license for export to restricted countries or denied parties. ITAR applies to defense-related semiconductor technology with more stringent controls, so a deemed export analysis of sharing controlled technology with foreign nationals in the U.S. should be part of licensing due diligence, alongside the Entity List and foreign-produced direct product rules.

Export control compliance is a mandatory element of any semiconductor IP licensing transaction involving foreign persons or entities. The Export Administration Regulations (EAR) administered by the Bureau of Industry and Security (BIS) control the export, re-export, and in-country transfer of dual-use items, including semiconductor design tools, technical data, and technology on the Commerce Control List. IP cores, RTL files, and design methodologies for advanced processors can be controlled under ECCN categories requiring a license for export to restricted countries or denied parties. The International Traffic in Arms Regulations (ITAR) apply to defense-related semiconductor technology — including chips designed for military radar, guidance systems, or communications — and impose more stringent controls, including registration requirements and restrictions on foreign national access even within the United States. Gurpreet Bal advises semiconductor IP licensors that a deemed export analysis — determining whether sharing controlled technology with a foreign national employee or contractor in the U.S. constitutes an export — should be part of any IP licensing due diligence. The BIS Entity List and the expanded foreign-produced direct product rules have added significant complexity to licensing decisions involving Chinese fabless design companies and foundries.

How do patent pools, FRAND obligations, and cross-licensing work in semiconductors?

Standard-essential patents carry FRAND licensing obligations for members of standard-setting organizations, and in semiconductors this is most acute for wireless connectivity IP, where royalty stacking across a large portfolio is a real cost challenge. Patent pools offer a way to license pooled SEP portfolios at a negotiated rate and reduce litigation risk, but pool membership is voluntary and major holders license independently. Cross-licensing, where companies exchange portfolio licenses often with a balancing payment, remains the dominant mechanism for resolving mutual exposure, and its field-of-use, scope, term, and future-patent terms require careful attention.

Standard-essential patents (SEPs) — patents that must be practiced to implement a recognized technical standard — carry FRAND (fair, reasonable, and non-discriminatory) licensing obligations for members of standard-setting organizations (SSOs) such as IEEE, ETSI, and the Wi-Fi Alliance. In the semiconductor context, FRAND licensing is most acutely relevant for wireless connectivity IP: Wi-Fi (IEEE 802.11), Bluetooth (Bluetooth SIG), and cellular (3GPP) standards are implemented in virtually every connected chip, and the royalty stacking problem — the aggregate of all FRAND royalty demands across a large patent portfolio — is a significant cost management challenge. Gurpreet S. Bal advises that patent pool licenses (Via Licensing for Wi-Fi, Avanci for cellular IoT) offer a mechanism for obtaining a license to pooled SEP portfolios at a negotiated rate, reducing transaction costs and litigation risk, but pool membership is voluntary and significant SEP holders (Qualcomm, Ericsson, Nokia, InterDigital) license independently. Cross-licensing — where two companies exchange licenses to each other's patent portfolios, often with a cash balancing payment — remains the dominant commercial mechanism for resolving mutual patent exposure between large semiconductor companies, and the structure of cross-license agreements (field-of-use, product scope, term, and the treatment of future-acquired patents) requires careful attention to avoid inadvertently licensing competitor products or constraining future portfolio strategies.

Gurpreet S. Bal is a Partner at Foley and Lardner LLP in Silicon Valley, where he advises technology companies on licensing, venture financings, M&A, and corporate transactions. He has represented clients in hundreds of transactions with aggregate deal value exceeding $60 billion across AI, semiconductors, fintech, and emerging technology.